As opposed to planar complementary metal oxide semiconductor (CMOS) devices, vertical field effect transistor (VFET) devices are oriented with a vertical fin channel disposed on a doped bottom source and drain and a doped top source and drain disposed on the vertical fin channel. A gate is present along sidewalls of the vertical fin channel. Advantageously, VFETs are being explored as a viable device option for continued CMOS scaling beyond the 7 nanometer (nm) technology node.
The process flow for a VFET has strict constraints on the thermal budget for downstream processing steps such as top source and drain epitaxy, junction anneal, and dopant activation anneal because the high-κ metal gate is already in place. As a result, undoped regions are inevitably formed at the tops of the device between the vertical fin channel and the top source and drain.
The high resistance in these undoped regions severely degrades device performance. The impact becomes even more severe when the channel length is scaled for fins of a given height, i.e., reducing the channel length for fins of a given height will increase the length of the undoped region at the tops of the fins.
Therefore, VFET device designs and techniques for fabrication thereof with improved performance would be desirable.